Abstract
This work proposes an approach for modeling the efficiency of in-line inspection in semiconductor wafer fabrication. Clearly, improved quality generates increased quality output, and thus higher income from sales. Yet, it also requires increased fault detection enabled by more inspection capacity, and thus higher cost. This work investigates the efficiency of inspection by evaluating the gain from quality output against the corresponding cost incurred. It is based on a production model of wafer fabrication, where wafer lots are sampled for inspection following their process by machines. The inspection detects out of control performance and triggers machine repair. Thus, quality performance improves as a function of the rate of inspection and the duration of response. Based on Pareto efficiency, the inspection efficiency curve is developed illustrating the relationship between quality performance and inspection capacity. It exhibits that quality output, driven by reduced out of control performance, grows with inspection capacity at a slower pace. Furthermore, incremental quality output and incremental inspection cost determine the most efficient working point. This point designates inspection capacity, inspection rate, and resultant quality performance. The novelty of this work is in suggesting a quantitative model for designing the efficiency of inspection in wafer fabrication.
Original language | English |
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Pages (from-to) | 458-464 |
Number of pages | 7 |
Journal | Computers and Industrial Engineering |
Volume | 99 |
DOIs | |
State | Published - 1 Sep 2016 |
Keywords
- Capacity
- Cost
- Inspection
- Quality
- Semiconductor manufacturing
ASJC Scopus subject areas
- General Computer Science
- General Engineering