The ubiquity of FPGAs in security applications makes it imperative to design a secured Configurable Logic Block (sCLB) that is resilient to side channel attacks. In this paper we take a step toward secured FPGA by introducing new design circuit level methodology for the implementation of a sCLB. The security level of the sCLB is significantly enhanced by the design of its combinational part (LUT block) based on a Dual-Rail Precharge MUX (DPMUX). The sCLB was implemented in a configurable array and fabricated in 65nm CMOS technology. Silicon measurements proved the effectiveness of the approach. The security level was evaluated using advanced power analysis techniques. In particular, the number of secret bits that can be learned (mutual information) by a CPA attack dropped from 4 bits (out of 4) after 1200 power traces for a conventional LUT design to only 2.56 bits after 19.2M power traces.
- hardware security.
- secure FPGA
ASJC Scopus subject areas
- Electrical and Electronic Engineering