Ultra-low power consumption silicon photonic link design analysis in the AIM PDK

We demonstrate an optimized silicon photonic link architecture using components from the AIM PDK that achieves an ultra-low sub-pJ/bit power consumption with an aggregate bandwidth of 480 Gb/s. At the transmitter, micro-disk modulators are cascaded along a bus waveguide to select and modulate wavelength-division multiplexed (WDM) channels. At the receiver, micro-ring resonator (MRR) filters are thermally tuned to match the corresponding disks to select from the multiplexed channels. This link architecture yields an ultra-small footprint compared to Mach-Zehnder designs, improving the system scalability and bandwidth density. Additionally, using micro-resonators to select and drop the desired wavelengths from a single bus waveguide allows for straightforward integration with a frequency comb source. The energy performance of the design is optimized through sweeping over three key parameters: (i) optical power per channel, (ii) channel count, and (iii) bitrate. These parameters are the dominant sources for the crosstalk and power penalty in the link design. We identify ideal points in the design space which minimize the energy per bit while staying below the desired bit error rate (BER) of 10^-12 and maintaining a realistic aggregate bandwidth. Simulations in the Synopsys OptSim environment using the AIM PDK v2.5a models confirm the functionality of the system with a BER < 10^-12, acceptable for both high performance computing (HPC) and data center (DC) applications. Furthermore, optimizing the link energy consumption in the AIM PDK provides a clear path towards low-cost and high-yield fabrication suitable for application in HPC and DC systems.