Ultra-low power subthreshold flip-flop design

Sagi Fisher, Adam Teman, Dmitry Vaysman, Alexander Gertsman, Orly Yadid-Pecht, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations


In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing power consumption in low-frequency systems. This paper proposes two architectures for implementing Flip-Flop cells, designed to operate in the subthreshold region. Both cells integrate a Gate-Diffusion Input (GDI) multiplexer in their designs to minimize area and capacitance. Timing parameters of the Flip-Flops are calculated and techniques for improving the timing characteristics are proposed. The proposed designs are simulated in a standard 90nm process achieving a power dissipation of 8.4nW in a typical corner at VDD=300mV with a delay of 51.7nsec.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Number of pages4
StatePublished - 26 Oct 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan, Province of China
Duration: 24 May 200927 May 2009

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310


Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/TerritoryTaiwan, Province of China

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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