Voltage bias effect on the esr of ferroelectric ceramic capacitors

Hermann Haag, Florian Hämmerle, Shmuel Ben-Yaakov

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The effect of DC voltage bias on the ESR of ferroelectric ceramic capacitors was studied experimentally. It was found that the ESR is increasing with capacitor voltage in the range of 5% to 80% over the specified voltage range of the tested components. These results are opposite to the trend displayed by the online simulation tool offered by a ferroelectric ceramic capacitors manufacturer. The implications of the obtained results to the losses of ferroelectric ceramic capacitors used in switched mode power supplies are that the estimated losses and voltage ripple are larger when the capacitors are under voltage bias.

Original languageEnglish
Title of host publicationPCIM Europe-International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2020
PublisherMesago PCIM GmbH
Pages1849-1854
Number of pages6
ISBN (Print)9783800752454
StatePublished - 1 Jan 2020
EventInternational Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2020 - Virtual, Online
Duration: 7 Jul 20208 Jul 2020

Publication series

NamePCIM Europe Conference Proceedings
Volume1
ISSN (Electronic)2191-3358

Conference

ConferenceInternational Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2020
CityVirtual, Online
Period7/07/208/07/20

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